1. Field of the Invention
The present invention relates to a process for forming a protection device on a semiconductor substrate, and more particularly to a method for forming a protection device with slope laterals on a semiconductor substrate.
2. Description of the Prior Art
FIG. 1A is a top view of a conventional MOS mask read only memory (ROM), and FIG. 1B and 1C are cross sectional views along line A-AA in FIG. 1A. As shown in the figures, the MOS mask ROM comprises a P type silicon substrate 100, and linear N+ buried regions 101 and 102 are alternatively formed in parallel in one direction in the substrate 100. The linear N+ buried regions 101 and 102 are formed by ion implantation with phosphorous or arsenic atoms. The N+ buried region 101 forms a source region for a plurality of memory transistors (e.g. transistors xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d) and corresponds to a ground line of the mask ROM. The N+ buried region 102 forms a drain region for the transistors xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d and corresponds to a bit line of the mask ROM. Also, a gate oxide film 103 is formed over the substrate 100 and the N+ buried regions 101 and 102, and a plurality of parallel word lines 104 made of polysilicon are formed on the gate oxide film 103. Also, the word lines 104 are formed perpendicularly to the linear N+ buried regions 101 and 102 and serve as the gate electrodes of a plurality of memory transistors (e.g. transistors xe2x80x9caxe2x80x9d and xe2x80x9ccxe2x80x9d) in the mask ROM.
In the conventional MOS mask ROM mentioned above, the data stored in the ROM (i.e. a ROM code) is formed by selectively doping certain memory transistors with boron ions. Specifically, a photoresist is formed over the MOS mask ROM and boron is doped into selected transistors while using the photoresist as a mask, such process is referred to as a xe2x80x9ccode boron doping processxe2x80x9d. Since the threshold voltage VT of a boron-doped memory transistor increases and the threshold voltage VT of an undoped transistor remains the same, data can be read from the ROM based on the difference between the threshold voltages VT of the transistors. For example, a transistor having a high threshold voltage VT will not turn on when a voltage Vread (having a voltage lower than the high threshold voltage VT) is applied to its gate electrode (i.e. the word line 104). On the other hand, a transistor having a normal threshold voltage VT will turn on when the voltage Vread is applied to the gate electrode (i.e. the word line 104). The ROM may consider the transistors that do not turn on to output a logic xe2x80x9c1xe2x80x9d and may consider the transistors that turn on to output a logic xe2x80x9c0xe2x80x9d.
Referring to FIG. 1B, when performing the code boron doping process to form a ROM code, a photoresist 105 is formed over the word lines 104 made of polysilicon as a mask for the N+ buried regions 101 and 102. However, the photoresist 105 is not always in alignment with the N+ buried regions 101 and 102. The boron atoms will be implanted into one portion of the N+ buried regions 101 and 102, and then neutralize electricity of the doped portion of the N+ buried regions 101 and 102. Therefore, the current in the N+ buried regions 101 and 102 is reduced. While, a measure to overcome the problem of one portion of the N+ buried regions 101 and 102 being boron-implanted is to form a protection region 106 over each of the N+ buried regions 101 and 102, as shown in FIG. 1C. Then, the word lines 104 made of polysilicon are formed on the protection regions 106.
In general, a metal silicide, for example, a cobalt silicide, is formed on a polysilicon layer to be formed word lines 104 to increase its conductivity. However, when etching the metal silicide, the residue of the metal silicide, for example, cobalt residue, is readily left on each vertical sidewall of the polysilicon layer to be formed word lines 104, and the residue of the metal silicide is still left on these vertical sidewalls after the word lines 14 formed. As a result, there is an electric conductivity between two word lines 104, and then the electricity of the MOS mask ROM is fail, due to the reside of the metal silicide.
Accordingly, there exists a desirability to provide a method for forming a plurality of protection devices each of which with slope laterals on a semiconductor substrate with a plurality of buried diffusion regions formed therein. The slope laterals of the protection devices can facilitate etching away a metal residue left on the sidewalls of the word lines made of polysilicon formed on the protection devices after a silicide of the metal is formed on the word lines.
It is one object of the present invention to provide a method for forming a protection device with slope laterals on a semiconductor substrate, in which a first etching step and a second etching step are repeatedly and alternately performed on the substrate with a plurality of alternative first sacrificial layers and second sacrificial layers formed thereon. The first etching step and the second etching step respectively have different etching selectivity with respect to the first sacrificial layer and the second sacrificial layer. And thereby, a plurality of protection devices with slope laterals are formed on the substrate.
It is another object of the present invention to provide a method for forming a protection device with slope laterals. The slope laterals of the protection device can facilitate etching away a metal residue left on each sidewall of a conductive layer formed on the protection device.
It is still a further object of the present invention to provide a method for forming a plurality of protection devices each of which having slope laterals on a semiconductor substrate with a plurality of buried diffusion regions formed therein. Each of the protection devices is formed over each of the buried diffusion regions, and a conductive layer is formed on the protection devices. The buried diffusion regions are served as bit lines of a mask read only memory (mask ROM), and the conductive layer is patterned to serve as word lines of the mask ROM. By means of the slope laterals of the protection devices, a metal residue left on each sidewall of the word lines formed of the patterned conductive layer is readily etched away after the conductive layer is patterned to form the word lines.
In order to achieve the above and other objects, the present invention provides a method for forming a protection device with slope laterals. Firstly, providing a semiconductor substrate having a plurality of alternative first sacrificial layers and second sacrificial layers formed thereon. A first etching step is performed to remove one portion of each of the first sacrificial layers and thereby expose one portion of each lateral of the second sacrificial layers. Subsequently, performing a second etching step to remove one portion of the lateral of the second sacrificial layer. Then, repeatedly and alternately performing the first etching step and the second etching step until completely removing the first sacrificial layers and then obtaining a plurality of protection devices formed of the second sacrificial layers each of which having slope laterals.